1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection, and more particularly, to an ESD protection circuit and method thereof for large-signal circuits.
2. Description of the Related Art
FIG. 1A is a schematic circuit diagram of a conventional ESD protection circuit. Referring to FIG. 1A, an ESD protection circuit 100 installed at the output terminal of the output circuit 110 includes a clamping circuit 120 and two series-connected diodes Dp1, Dn1; meanwhile, both the output circuit 110 and the clamping circuit 120 are coupled between a first operating voltage Vdd and a second operating voltage Vss. The clamping circuit 120 includes an electrostatic discharge unit 130 and an ESD detecting circuit 140. The electrostatic discharge unit 130 includes a NMOS transistor TN, whereas the ESD detecting circuit 140 includes a resistor R1, a capacitor C1 and an inverter D1.
While an electrostatic current flows to the output circuit 110 through the output pad Po and voltage sources (Vdd, Vss), the ESD detecting circuit 140 triggers the electrostatic discharge unit 130 to bypass the electrostatic current without damaging the output circuit 110. However, the output voltage of a large-signal circuit or a power amplifier has a DC voltage component of about Vdd. Under normal operations, the magnitude of the output voltage reaches up to 2×Vdd (i.e., a voltage swing S equal to Vdd). On condition that there is only one diode Dp1 installed in the circuit, a voltage drop Vdd between Vout and Vdd will cause the diode Dp1 to turn on (the turn-on voltage of conventional diodes is approximately 0.7V) and a fraction of the output voltage Vout that is greater than (Vdd+0.7V) will be clipped, as shown in FIG. 1B.
In order to solve the above-mentioned problem, an ESD protection circuit is discussed in U.S. application Ser. No. 11/723,911, filed Mar. 22, 2007 and assigned to Realtek Semiconductor Corporation, a schematic circuit diagram of which is illustrated in FIG. 2. An ESD protection circuit 200, installed at the output terminal of a power amplifier 210, comprises a clamping circuit 120, an inductor L, a diode Dn1 and a diode string Dp1˜Dp5. Note that the diode string including five diodes Dp1˜Dp5 is merely taken for example herein; usually, a number M of diodes in the diode string is greater than or equal to the voltage swing S divided by the turn-on voltage of the diodes. If a positive ESD stress (with respect to Vss) appears at the output pad Po, the diode string Dp1˜Dp5 located between the output pad Po and the first operating voltage Vdd will be switched on and the clamping circuit 120 will be triggered to bypass the ESD current without damaging the power amplifier 210. Meanwhile, the voltage swing S of the output voltage Vout is no longer limited by the ESD protection circuit 200, therefore rendering a perfect symmetrical waveform.
In comparison with the ESD protection circuit 100, while the positive ESD stress appears at the output pad Po, the increased number of diodes Dp1˜Dp5 in the diode string causes the diode string to have an increased turn-on resistance Rd (or an increased conduction path length) and the NMOS transistor TN to have an increased turn-on time (this is because the turn-on time t=R×C1, where R denotes an equivalent resistance of the resistor R1 and the turn-on resistor Rd connected in series). This increases the probability that the ESD current flows to the power amplifier 210 and accordingly reduces the effectiveness of the protection provided by the clamping circuit 120 for the power amplifier 210.